Power and Data Telemetry for Implants in Biomedical and Robotics Application

TITLE: Power and Data Telemetry for Implants in Biomedical and Robotics Application (Completed)
Sameer Sonkusale
Zhenying Luo, Wangren Xu


Recently there has been a lot of attention to the development of batteryless implantable electronic devices for medical treatment and rehabilitation. These implant devices receive part or all of their power supply wirelessly from external equipment. At the same time, wireless data communication between the implant device and external equipment is also established. However wireless power delivery is usually not efficient, therefore low power consumption becomes a critical requirement for implant designs. In this project, a prototype of a batteryless implant device is being implemented, which demonstrates both the wireless power delivery and data communication.

We have currently demonstrated a class-E power amplifier for wireless power delivery that delivers 4 watts with a power efficiency of about 80%. For the data transmission from the implant to external device, LSK (Load Shift Keying) data modulation scheme is used for its ultra low power consumption requirement on the transmitter side. The LSK data rate is 100k bit/s. Both the class-E power amplifier and the LSK signal receiver are designed, analyzed and implemented on print circuit board (PCB). For the data transmission from the external device to the implant, BPSK (Binary Phase Shift Keying) data modulation is used. BPSK modulation has constant signal amplitude and carrier frequency, these elements helps to stabilize the wireless power coupling.

We have invented a novel low power high data rate BPSK demodulator architecture and verified it on silicon. Chip measurement results show that this architecture has low power consumption and robust performance. The first version occupies 0.1mm2 area and consumes 5mW power from a 3.3V power supply generated using an LDO. Based on theoretical analysis, several improvements to the BPSK demodulator have been proposed and simulated for performance. The new implementation will considerably reduce the power consumption to about 1.8mW.

Schematic circuit diagram diagram
Figure1: BPSK Demodulator Architecture: 1st version and the microphotograph


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