Simulation with Verilog-XL


Verilog-XL is a great tool to perform digital logic design. It lets you perform logic design at the functional level. This enables a designer to test his logic without going into gory details of the transistor level operations. More details about this tool and its syntax can be found by using the openbk command at the prompt. This section will enable you to create a verilog file for your design (an example considered here is that of an inverter).  You will also simulate this inverter using Cadence.

Just as schematic and symbol, functional view is the verilog description of the cell. As you can recall, that schematic is a transistor level description of a cell, symbol is a symbolic input-output description of a cell.  To create a functional view, you can either perform 1 a. below or 1 b. below.

1. Do either 1 a. or 1 b.

        1 a. This will explain how to open a functional view for a cell, for which the schematic has already been drawn. To do this, go to the schematic window and select

     Create Cellview ->From Cellview... from the Design menu.

A pop up window will appear.  Select the Tool/Data field as Verilog-Editor and write functional in the To View Name field. Sometimes functional will automatically get written to that field, after you choose Verilog Editor in the Tool/Data field.

creat verilog

1 b. You may go to Library Manager Window, Click on File -->New-->CellView. You should get the same window as given in 1 a.

2.  After a while, an text editor window will pop up as shown below. 

verilog edit

You need to prepend the following lines to it:

`resetall
`celldefine
`delay_mode_path
`timescale 1ns/10ps

     Then append the following to the same functional view:

`endcelldefine

     Add the following the statement in between the module statements:

not (out, inp);

     If the input and output names are not “inp” and “out” for you, substitute them with your own names.  The (out, inp) syntax specifies the output and input for the inverter.   In Verilog, the convention is that the output arguments of the module (gate) are listed before going on to the inputs.  The convention is strictly observed in all Verilog-XL primitives.  An example of the functional view is shown below.

verilog edit

    Save the functional view and close it.  Cadence will tell you in the CIW whether the functional view is successfully parsed (no syntax errors) or not.

3.  With the schematic window of the cell you want to simulate open, select Tools --> Simulation --> Verilog-XL

4. A pop up menu will appear. Specify the path in which you want to run the simulation.  The author has chosen ~/tmp/my_inverter.run1 as the Run Directory.(make sure you have create a tmp directory in your home directory). Change the View from schematic to functional.  Then click on the OK button.  Please note that the view must be changed to functional in order for Verilog to simulate using the functional view and not the schematic view.  You should realize that the schematic and the functional views are only related to each other in terms of input/output pins and not in terms of connectivity.

vlg sim setup

5. A pop up window will appear.  This window is called the Verilog-XL Integration Control window.  Start the simulation process by first clicking on Setup -> Record Signals in the Verilog-XL Integration window.  Make sure to choose All Signals as shown below.


Next, click on the top-left button in the list of buttons provided in the Verilog-XL Integration Control Window or select Simulation -> Start Interactive.

vlg ctl window



6.  Click on the Stimulus -> Verilog button. You will get the Stimulus Options window as shown below. Select the "Edit" button and press OK. This will help you create a stimulus file for the simulation of an inverter.

stimulus

An Text Editor window will appear. Modify the file as shown below

stimulus edit


The above stimulus file starts with the input inp = 0 and then changes to 1 at the time instant 25. Then it changes to 0 at 35 time instants later  (25+35=60 time instants) and then to 1 at 75 instants (25+35+75=135 time instants) later. The simulation time is 235 units. The exact time of simulation is governed by the timescale command in the original functional view file. After you finish editing, select Stimulus -> Verilog again. Then this time click the "Select" button in the window that appears. This is to select the testfixture.verilog file that you just edited to be your stimulus file.

7.  Click on the Continue icon (second top icon in the second column) in the Verilog-XL Integration Control window or select Simulation -> Continue.  The Verilog simulation will begin.  Pay attention to the messages that appear in the Verilog-XL Integration Control window to verify that the simulation is indeed running.  You will be notified by those messages in the window when the simulation has finished.

NB.  This is where Cadence begins to act strangely; to ensure that Verilog is using the correct stimulus file that you just edited, repeat the above steps, starting from Step 5, one more time.  At each step, make sure the stimulus file is indeed the one you wanted.  You can do so by clicking on the View File button of the Stimulus Options window (Stimulus -> Verilog).

8) Upon completion, your Verilog-XL Integration Control Window should look like this.

 

 

 

Click on the View Waveforms Icon on the bottom right of the icons section on the left side of the window. This will open up SimVision which shall look like the window below.

 

 

9.  Select File -> OpenDatabase , a pop-up window of open database as shown below, go to directory '~/tmp/my_inverter.run1/RunObject.0/ShmDir/shm.db/" and highlight 'shm/trn' and press 'Open' button to open it.

A window as shown in the picture below will appear, click on the 'test' and you'll see two signals, which are 'inp' and 'out', in the right panel (some displays will show them at the bottom of the window).

 

You should be able to plot the signals of interest from the above design browser.

ADDITIONAL DESIGN GUIDELINES:

If you are interested in performing verilog simulation on a complex logic gate or any complex digital system, you DO NOT have to write the verilog code for the entire complex logic gate. As long as you have verilog functional modules for each cell used in the design at some hierarchy within the cell, you should be able to perform verilog simulation from the schematic window directly. Follow this link for an example.

 

 



previoushomenext

Sameer Sonkusale, Usman Khan, Jiong Xie, Septemebr 2005,
Questions: Email sameer@ece.tufts.edu