Post Layout Simulation

The parasitic capacitances extracted according to how your layout is designed might be critical in affecting the actual performance of your design.  In order to get an idea of how the design would work from your layout, you should perform a post-layout simulation from the extracted view.  The procedure is identical to that for simulating from the schematic view.

1.  Open up the test schematic for the inverter in edit mode.  Under the Tools menu, choose Analog Environment. A window similar to the one shown below will pop-up.

Figure 1 Analog Design Environment

The steps are very similar to the ones mentioned previously in the spectreS portion of this tutorial.  However, the one change that needs to be made is in the Setup menu of the Analog Environment simulation window.  Click on Setup -> Environment… and you will see the Environment Options window open up.  Originally, the Switch View List should contain the following items:

spectreS spice cmos_sch cmos.sch schematic

As shown in Figure 2,in order for Cadence to simulate through the extracted view of the layout design instead of the schematic view, you will include an additional item (analog_extracted) in the Switch View List such that it now contains the following:

spectreS spice cmos_sch cmos.sch analog_extracted schematic

Figure 2 Environment Options
2.  You can now perform the simulation in the same manner as before.Don't forget to setup model path as shown in Figure 3. This additional step allows you to take into account all the parasitic capacitances (eg. from interconnects and source/drain areas) that were extracted into the extraction view from your layout design.  You may be able to notice subtle differences in the post-layout simulation results or waveforms as compared to the pre-layout schematic view results. To be absolutely sure that Cadence is running simulations through the extracted view, you can view the generated spectreS netlist by clicking on Simulation -> Netlist -> Display Final … from the Analog Environment Simulation window.  The generated netlist will open up in another window.  From the generated netlist, you can easily tell that the netlist is of extracted schematic.

Figure 3 model path configuration


Adapted from  Sameer Sonkusale's  Cadence tutorial of IC 4.4.3   by Jiong Xie on Nov. 15, 2004