The parasitic capacitances extracted according to how your layout is
might be critical in affecting the actual performance of your
order to get an idea of how the design would work from your layout, you
perform a post-layout simulation from the extracted view. The
is identical to that for simulating from the schematic view.
1. Open up the test schematic for the inverter in edit
Under the Tools menu, choose Analog Environment. A window similar to the
below will pop-up.
Figure 1 Analog Design Environment
Figure 2 Environment Options
The steps are very similar to the ones mentioned previously in the
of this tutorial.
However, the one change that needs to be made is in the Setup
the Analog Environment simulation window.
Click on Setup -> Environment…
will see the Environment Options
window open up. Originally, the Switch
View List should
contain the following items:
spectreS spice cmos_sch cmos.sch schematic
As shown in Figure 2,in order for Cadence to simulate through the
extracted view of the layout
design instead of the schematic view, you will include an additional
in the Switch View List such that it now contains the following:
spectreS spice cmos_sch cmos.sch analog_extracted
2. You can
now perform the simulation
in the same manner as before.Don't forget to setup model path as shown
in Figure 3. This additional step allows you to take
into account all the parasitic capacitances (eg. from interconnects and
source/drain areas) that were extracted into the extraction view from
layout design. You may be able to
notice subtle differences in the post-layout simulation results or
compared to the pre-layout schematic view results.
To be absolutely sure that Cadence is running simulations through the
extracted view, you can view the generated spectreS netlist by clicking
on Simulation -> Netlist -> Display
Final … from
the Analog Environment Simulation window.
The generated netlist will open up in another window. From the generated netlist, you can easily tell that
the netlist is of extracted schematic.
Figure 3 model path configuration