1. The first step is to extract all the connectivities and
capacitances from your layout design. From the layout view window,
choose Extract... under the Verify
menu. A window will pop-up. Make sure that the entries are as given
below. For the entry in Switch Names, click on Set Switches. A
will pop-up. Choose the option for Extract_parasitic_caps.
Note that, if for some reason, you did not want to extract the
capacitances, you would leave the Switch Names empty. Finally, click on
OK. The beauty of this extraction
tool is that Cadence will recognize not only all the connections but
importantly, if you have designed the layout correctly, it will also
all the nmos and pmos transistors.
Make sure that your layout window is in Edit mode.
2. Your layout will then be extracted and
is doing so, the intermediary steps will be displayed in the CIW.
It will tell you whether the extraction is successful or not.
Allow FET Series Permutations, Combine Parallel FETs, Combine Parallel Capacitors, Compare FET Parameters
This check should be performed every time you are about to start an LVS.
3.c. From the extracted window, choose LVS...
under the Verify menu. A pop-up
appear. Type in the Run Directory that you want to run the LVS
well as the cell names that you want to run LVS on and all the other
shown in the inverter example below. It is advisable to put the run
in the /tmp/username as you might run
disk quota when designing huge layouts. If you already had an
LVS directory, a window will pop-up which might say " The selected
LVS rule directory does not match the run form". Just select Form Contents and click OK.
Click on the OK button.
5. We see from the si.log file above that there are no errors
in the LVS comparison. However, there could have been errors if, for
example, the W and L values of the transistors in the schematic window
did not match with the W and L values of the transistors in the
layout. If there are any errors, click on Error Display in the LVS menu to view
what went wrong. It is very beneficial if you click on Info in
LVS window shown above. It will explain each of the terms in the
above window in great detail. The si.log will also explain to you all
the errors that it detected in both the schematic and layout views
during the LVS comparison.
The following points illustrate a situation if we had an error in the previous step.
6. By clicking on Error Display in the LVS window, the LVS Error Display window will pop-up. Select or deselect the various options so that the errors that will be shown are only those that you want to see at this point. In our case, the only errors we encounter is the size errors and to see that, we select parameters under the Unmatched field.
7. To zoom into each error, select the Auto-Zoom option and then click on the First button from the Display buttons. To view each error in sequence, keep clicking on the Next button. You will see each error being highlighted by whatever color you selected from the Error Color menu in the extracted window. The default color should be “hilite.d1”. You should pick a color that is easy for you to see in the extracted view.
8. To get more information about the error, click on the Explain button. Then move your cursor above the highlighted point/area and click on the left mouse button. A pop-up menu will appear. Sometimes the information given is not very helpful. This is where your problem-solving skills come to play and are being sharpened.
9. Modify the layout or schematic appropriately and rerun the LVS check till your layout design is perfectly matched to the schematic view.
10. There is also a feature that can help you in debugging the layout; especially in checking the connections of your nets. Move your cursor to the net you want to highlight and click on the left mouse button. Anything that is connected to that net will be highlighted in white. You are then able to determine which connection or connections should not have been made to that net based on what has been highlighted. An example of the highlight is shown below.
11. When LVS reports that the netlists match, return to the LVS setup window and click the "Build Analog" button. Click "OK" in the resulting dialog box. This will create a new view in your library called "analog_extracted," you will need this file when you perform post layout simulations.