You would have known how to enter and simulate your designs using Verilog-XL and Spetre. The next step in the process of making an integrated circuit chip is to perform a layout. What is a layout? A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your devices because it determines whether yours is a working design or a flop!
There are 2 ways to doing a layout: manual and automated. Manual layout usually enables the designer to pack his devices in a smaller area compared to the automated process but it is more tedious. The automated process, on the other hand, is done using standard cells and usually takes more real estate space but it is much faster. In this tutorial, you will learn how to perform MANUEL LAYOUTS ONLY and a simple inverter layout will be shown. You should know that for the purposes of this course, you are required to know how to design manual layouts, even though Cadence can accommodate either manual or automated layouts.
Before we get into the layout, first you need to understand the design rules for layout. The design rules that we will be using are the MOSIS Scalable CMOS Rules. Design rules gives guidelines for generating layouts. They dictate the spacings between wells, sizes of contacts, minimum spacing between a poly and a metal layer and many other similar rules. Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. The design rules that we will be using can be obtained from the following link on MOSIS Layout Design Rules(you should look for SCN4ME as technology code). Note that the layout is very much process-dependent, since every process has a certain fixed number of available masks for layout and fabrication. For the case of this tutorial, we are using an AMI 0.60u CMOS process, which is a nwell process and supports two poly and three metal layers.
Before we proceed any further, please make sure that your present library is associated with a techfile. If you had followed this tutorial for your design of an inverter, then you might have already associated a techfile when you created a library ee103 in the first place. Otherwise, you can still do it, by clicking on the middle button by placing the mouse on the library name in the library manager window. There is an option for "Attach Tech Library". Once you choose that option, click on AMI 0.60u C5N (3M, 2P, high-res) as your process.
1. Create a layout cellview of the cell. Here we will create a
layout for the inverter cell.
In the library manager window, click on the File -> New -> CellView. Choose CellName as inverter and View Name as layout. Then click on the OK button. An empty layout editor window will pop-up along with a LSW window. The LSW window will show all the layers such as nwell, pwell, active, etc. for the given process. An alternate way to open the layout editor window is to type “layout” into the View box of the inverter cell in the Library Manager window. A “Create New File” window will pop-up. Change the Tool item from “Composer-Schematic” to “Virtuoso” and make sure the View Name is “layout”. If not, manually change this by typing this in.
If you don't see the above (not necessary to be in the above order) you will need to set the mask layers manually. To do this, go to Edit -> Set Valid Layers and select/deselect the masks. Make sure that you at least have the following masks in your LSW window.
nwell, nselect, pselect, nactive, pactive, poly, elec, metal1,
metal2, metal3 (all dg's) & metal1, metal2, metal3 (pn's).
2, Since we are using the AMI 0.60u technology, we only have an nwell process to use. Thus, the substrate will be a p-type
substrate. We can always assume that the background is a p-substrate.
Now we will create a pmos transistor first. Here we going to use
some layout templates from 'NCSU_TechLib_ami06'
library to draw layout. In Virtuoso window, i.e. layout editor
window, press 'i'( or click on
add instance icon), a 'create instance'
dialog window pops up, then click on 'Browse' button, a 'Library
Browser' window shows up, select the right cell you want to add as
shown in figures below. As shown in Figure 2, you can change parameters of a newly created cell by entering the correct size
information when you create one, for example, I specified the width of
pmos be 4.5u by modifying 'Width(grid units)' to 30 such that the pmos is 3
times wider than nmos.
Figure 2, Create Install Dialog
Figure 3, Library Browser Window
Click on 'OK', you will place a pmos on layout editor window. These
will appear as a black box. To see through the cell, type "Shift -f".
This will make the cell visible. Remember that you cannot update this
cell, since it is a standard library cell. Add a 'NTAP', which is used
to connect bulk of pmos, next to the pmos.You will get something like
Figure 4.The green-shaded rectangle is the nwell layer, the green perimeter is nselect and
the orange perimeter is
pselect. The numbers represent the length in um (micrometers).
Therefore, for the AMI 0.60u technology, lambda = 0.3u and 2*lambda =
0.6u. The editor options have been defaulted such that every cursor
advancement corresponds to 0.15u or 1/4th the 2*lambda feature
size. The ruler shown above can be invoked by typing
k. It can be removed by
typing capital K (shift+k).
They show the length in micrometers. Note
that you do not have to necessarily follow the dimensions shown above. In fact, it is probably a good idea to play
around with the lengths and widths in order to see how small a mask
layer you can create without violating any of the design rules.
Figure 4 step 1 of layout
The LSW window will be used to draw the masks in the layout editor window. To draw a mask, say an nwell layer, first choose the corresponding layer in the LSW window by clicking on the layer. Then, move your cursor into the layout window where you want to draw the nwell layer and type r (rectangle) and move your mouse. A yellow box will appear indicating the boundary of the nwell mask. Just click on the left mouse button to draw the nwell rectangle; we'll worry about the actual dimension later. To change the dimension of the rectangle, move your cursor to the side where you want to extend or shorten such that the side is highlighted and then type s (stretch). The side will move with your cursor.
3, Likewise, draw nmos and ptap as shown in the figure below. Make sure that you align two transistors in the center so that you can connect gates by nice poly line.
We have chosen to space the nmos and the pmos by the distance of 9um
selective-to-selective distance for a 0.60um process. This region
between the two transistors would be used for pin definitions and for
routing signals from one layout cell to another. The more the distance
between the nmos and the pmos transistor, the more connections can be
routed and less problems to worry about in the future when designing
big cells. However, a large distance may be inefficient and result in a
very big layout. But for the sake of learning, we would rather choose
to go with a large distance of around 9um. Please refer
charpter 5 in textbook to make yourself understand standard cell
concept, which requires that different cells have similar height
between two power supply rails so that you can place them side by side.
Note that you can stretch the distance between the active layers to
make the cell shorter. One way would be to
use the s command on the poly and
metal1 vertical strip layers to stretch the layers upwards. You can then move the rest of the nmos
transistor up by highlighting the bottom portion of the layout with
your mouse (all of the edges will be highlighted in white) and using
the m (move) command.
Once you are in the move mode,
just click once on the highlighted portion of the layout and move it
upwards. Click again to release the selected layers. A good way to know
if you are in the move mode is to
look at the lower left-hand corner of the inverter layout view and read
the messages there. You should see the
following: Select the figure to be moved:
6. The gate of the transistors needs to be connected to the metal1 lines for it to be accessed. To do that you will be using a contact "cc.dg" to make a contact between an already overlapping metal1 and poly layer. Similarly, we desire to then connect the metal1 to metal2 (though it is not necessary) for pin connections. For this purpose, we will make a contact between a metal1 and a metal2 using a "via". There are two ways of doing this.
Method 1: Go to 'NCSU_TechLib_ami06 library' to select cell " m1_poly" (note capital letters), which means metal 1 to poly, Similarly, to access a metal1-metal2 combo with a via, instantiate the cell "m2_m1" from the libray .<>Method 2: Bring metal1 and metal2 to overlap each other and then draw a "via.dg" rectangle of 2lambda * 2lambda (which is 0.6u*0.6u for AMI 0.60u CMOS process). Similarly, bring poly and metal1 together and then draw a "cc.dg" rectangle of 2lambda * 2 lambda.>
The figure below shows the
connection. The red-shaded polygon with a black square at
the center and blue borderline is the m1_poly contact. The blue-shaded
polygon with a pink square at the center and pink borderline is the
Note that at any time, you can view the properties of any layout element you placed in your layout view by highlighting the particular element with the mouse and using the p (properties) command. This is especially helpful when you want to identify a particular via or pin that you have just created.
There are many other useful layout commands and features available through Cadence and most of these options have their own hotkeys. A very good idea would be to take a little bit of time to go through the many layout functions in the menus located at the top of the layout view (eg. Window, Create, Edit, Connectivity, Options) and maybe even try some of them out on your initial layout design. You can always undo your last performed function by clicking on Edit -> Undo or by pressing the u button.
Here are some hotkeys that I have found to be very useful when designing layouts:
Move about the layout view screen – keyboard arrows (up, down, left, right)
Fit entire layout onto screen – f
Zoom in/out – Ctrl/Shift z
Save design – F2
Cancel previous command – Esc
Reveal all mask layers within each layout cell – Shift f (Use Ctrl f to hide these layers)
Properties – q
Create path – p (Convenient for making interconnections between I/O pins of layout cell; need to select mask layer first from LSW window)
Create rectangle of mask layer – r (Select .dg mask layer first from LSW)
Create pin – Ctrl p (Select .pn mask layer first from LSW)
Instantiate layout cell – i
Select more than one mask layer simultaneously – Hold down Shift and click on each layer (Use Ctrl to deselect a particular layer)
Undo - u
Copy – c
Delete – d
Move – m
Stretch – s (Point to edge of mask layer first using mouse cursor)
Ruler – k (Erase ruler – Shift k)
CONGRATULATIONS!!! You've just created your first inverter, graphically that is....
When working with routing different cells and in the design of bigger cells, please make sure that you pay attention to the following issues:
1. Avoid using polysilicon (poly) as a long wire. Use it only for local, < 6 um, connections since its sheet resistance is quite high (15-30 Ohms/square), as well as its capacitance over field oxide.
2. Use thick wires for power rails, minimum 4 lambda, especially if they are long and supplying a lot of current. Keep in mind that the typical current density rating for metals is 0.5 mA/micron. Size them appropriately for the value of the current they carry.
3. When changing metal layers,
the number of contacts to use should follow from the current rating of
the contacts themselves. The current density for each
contact should be kept below 0.5 mA/micron.