EE 103
(Introduction to VLSI Design)
User's Guide to Cadence
IC 5.0
Setting
Up Your Unix Environment
Starting
Cadence
Create
Libraries
Schematic
entry using Composer
Create
Symbols
Simulation
with Verilog-XL
Simulation with SpectreS
Custom Layout using Virtuoso
Design Rule Check (DRC)
Layout Versus Schematic (LVS) Verification using Diva
Post Layout simulation using SpectreS
Inserting
I/O pads and Submitting the Design to MOSIS
Adapted
from Sameer Sonkusale's Cadence
tutorial of IC 4.4.3 by Jiong Xie on Sept. 13, 2004