Design Rule Check (DRC)

Our next step in the Design Process is to perform a Design Rule Check, more commonly known as DRC, on the layout.  Although designers might be conscious of the design rules when performing the layout, there is a possibility of overlooking and thus violating the design rules.  So, the DRC is a step taken to prompt us of any violations.  This step is important because the violation of any design rules would result in a higher probability, and in some cases an absolute certainty, that the fabricated chip does not work as desired.

1.  To run the DRC, choose DRC... from the Verify menu in the layout view window. A pop-up menu will appear.

You need to make sure that you're in edit mode for your layout that you want to run DRC on. For huge layouts, DRC might take a bit of time to perform.  You can shorten this time by deselecting the Echo Commands option.  Click on the OK button.

  2.  Cadence then runs the DRC and reports the errors or warnings, if any, in the CIW window.

The CIW window above shows that there are no errors or warnings found in the DRC process.

3.  Let's perform a DRC on a layout that has errors. For the purposes of this tutorial, this step is strongly recommended so that you can gain some experience in dealing with layout DRC violations.  You can purposely violate a design rules by moving contact closer or stretching/shifting one mask layers to some ridiculously large dimension as shown below. In this case, the space between two active contact are not big enough and the via is slightly bigger than 2 lambda * 2 lambda .

The layout above leads to the results of the DRC.  Errors are indicated by markers (white as shown above) but in your layout, these markers will blink.  The errors are also reported in the CIW as shown below.

4.  You may then proceed to correct the errors according to the design rules. Taking the above as an example, SCMOS Rule 7.2.a states that the minimum spacing between any two metal1 layers is 0.6 um.

5.  When performing huge layouts, the blinking markers might not be easily located at times.  Fortunately, Cadence has an easy search tool.  Under the Verify menu in the layout window, choose Markers -> Find...

A pop-up menu will appear.  Click on the Zoom to Markers box.

Click on the Apply button and Cadence will zoom in to the errors or warnings as desired.  If there are more than one errors/warnings, as is almost always the case, you can view each one of them by clicking on Next.


Adapted from  Sameer Sonkusale's  Cadence tutorial of IC 4.4.3   by Jiong Xie on Nov. 15, 2004